Improved circuit for detecting the passage of an article beating a repetitive marking

ABSTRACT

The apparatus disclosed relates to a circuit arrangement for detecting the passage of an article bearing a repetitive marking adapted to repetitively alter the reflectance of light impinging on the marking as the article is transported through an examination station. The arrangement includes a first circuit including a photosensitive device positioned at the examination station for impingement by light which is reflected from an article being transported through the station and adapted for generating an alternating signal as the article is transported having a frequency corresponding to the frequency of the repetitive markings on the article. A second circuit provides an output signal proportional to the integral of the signal during the transit of the article from the examination station. A third circuit disables the integrating circuit in the absence of an article at the examination station and enables the second circuit to form the integral of said alternating signal during the transit of the article through the examination station. A comparator circuit is included for providing a first DC output level when the amplitude of an input signal applied thereto exceeds the amplitude of a reference signal applied thereto, and for providing a second DC output level when the amplitude of the input signal is less than the amplitude of the reference signal. Further apparatus is provided for coupling the integral of the alternating signal from said integrating means to the first terminal of said comparator and for applying a reference potential to said second input terminal.

United States Patent 1 1 Carnes et a1.

[ 1 Nov. 25, 1975 IMPROVED CIRCUIT FOR DETECTING THE PASSAGE OF AN ARTICLE BEARING A REPETITIVE MARKING [75] Inventors: W. Robert Carries, Darien; John J.

Balogh, Jr., Trumbull; Lester L. Selnick, Ridgefield, all of Conn.

[73] Assignee: Pitney-Bowes, Inc., Stamford, Conn. [22] Filed: Apr. 2, 1974 [21] Appl. No: 457,395

{52] US. Cl 235/183; 235/6111 E; 250/565;

250/568; 250/571 [51} Int. Cl. G06G 7/18; (306K 19/06 [58] Field of Search 235/183, 61.1] E;

340/1463 Z, 146.3 AC, 146.3 AE1250/224, 559, 560, 565, 571, 556; 209/l11.7

[56] References Cited UNITED STATES PATENTS 3,246,295 4/1966 DeClaris et al. 340/1463 3,564,268 2/1971 Bayne et a1 250/556 3,636,332 1/1972 Nelson et al .1 235/183 3,758,752 9/1973 Kapsambelis et all 235/61 .11 E 3,787,689 1/1974 Fidelman 250/560 Primary ExaminerFelix D. Gruber Attorney, Agent, or Firm-William D. Soltow, Jrx, Albert W Scribner; Robert S. Salzman [57] ABSTRACT The apparatus disclosed relates to a circuit arrangement for detecting the passage of an article bearing a repetitive marking adapted to repetitively alter the reflectance of light impinging on the marking as the article is transported through an examination station.

The arrangement includes a first circuit including a photosensitive device positioned at the examination station for impingement by light which is reflected from an article being transported through the station and adapted for generating an alternating signal as the article is transported having a frequency corresponding to the frequency of the repetitive markings on the article.

A second circuit provides an output signal proportional to the integral of the signal during the transit of the article from the examination station.

A third circuit disables the integrating circuit in the absence of an article at the examination station and enables the second circuit to form the integral of said alternating signal during the transit of the article through the examination station.

A comparator circuit is included for providing a first DC output level when the amplitude of an input signal applied thereto exceeds the amplitude of a reference signal applied thereto, and for providing a second DC output level when the amplitude of the input signal is less than the amplitude of the reference signal. Further apparatus is provided for coupling the integral of the alternating signal from said integrating means to the first terminal of said comparator and for applying a reference potential to said second input terminal.

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US. Patent Nov. 25, 1975 Sheet 11 of 11 3,922,539

AN IMPROVED CIRCUIT FOR DETECTING THE PASSAGE OF AN ARTICLE BEARING A REPETITIVE MARKING This invention relates to apparatus for automatically sorting unfit currency from fit currency. The invention relates more particularly to an improved apparatus for enhancing the sorting procedures and for increasing the security against loss or theft of currency during the procedure.

Currency which has been in circulation for a period of time becomes soiled, worn, and at times damaged and is no longer considered fit for continued use. The unfit currency is removed from circulation and is destroyed. Federal Reserve Banks throughout the United States have been assigned the responsibility of separating the fit from the unfit currency which is forwarded to them from correspondent banks. After sorting, unfit currency is batched and is transmitted to the Bureau of Printing and Engraving for destruction.

Many millions of dollars in unfit currency is removed from circulation daily and the examination and sorting of this currency becomes a significant task. In practice, currency is sorted manully by trained workers at the Federal Reserve Banks. The segregated unfit bills are then demonetized by marking or mutilating in a distinctive manner prior to destruction.

The transmittal. handling, accounting and security of currency has been accomplished by a procedure developed over the years whereby currency is collected into bundles or straps. A strap of currency, which is generally bound together by a paper belt, typically contains 100 bills of a same denomination. At times, the strap can contain a lesser or greater predetermined number of bills. During the fitness sorting procedure, an original strap is broken by a worker; the bills of the strap are visually examined; and the bills are regrouped into a pile containing only fit bills and a pile containing unfit bills. Upon depletion of an original strap of bills, the bills in the fit and unfit piles are counted in order to verify that the original strap contained a full complement of bills. After verification of the count, straps of fit bills are formed for recirculation while straps of unfit bills are formed for subsequent demonetizing and destruction. The demonetizing is then subsequently accomplished by breaking a strap of unfit bills, permanently marking or mutilating the bills, recounting the demonitized bills and again forming the same into a strap for transmittal to the Bureau of Printing and Engraving for destruction.

The described fitness sorting and demonetizing process is disadvantageous in several respects. Although workers are trained for making a visual examination of the fitness of a bill, the determination is a subjective one which is made during a tedious repetitive process and the results often vary significantly within a Federal Reserve Bank and between the different Federal Reserve Banks. In addition, the necessity for establishing an accurate accounting and security for fit, unfit and demonetized bills further complicates the overall fitness examination and demonetizing procedure.

Nonetheless, the use of the strap procedure for transmitting and handling currency has merits which recommend its continued use. It would be desirable however, to automate some of the manually performed tasks with a method and apparatus which is compatible with this procedure. While machine methods for sorting fit and unfit currency and for demonetizing unfit currency are known, these methods are generally complex, expensive, time consuming and are either incompatible or inconvenient for use with the strap procedure of handling currency. In addition, they are susceptible to defeat by defects the currency or in the handling of the currency which heretofore were correctable by a worker during a manual sorting process or which, by virture of the manual nature of the handling, did not occur. These defects are, for example, the adhesion of one bill to another; the overlapping of successively fed bills at an automated examination station, and the severe mutilation of bills being examined. Furthermore, known apparatus for the demonetizing of unfit bills have not provided the degree of security necessary to guarantee against the theft of unfit currency and the unauthorized reintroduction of demonetized currency into circulation.

In copending US. Pat. application Ser. No. 457,366 which is filed concurrently herewith and which is assigned to the assignee of this invention, there is disclosed and claimed and improved method and apparatus for sorting fit and unfit currency.

An object of this invention is to provide in a currency examination apparatus, an improved electrical means for accounting, sorting and separating currency into straps, and causing a verifiable display of the results of these steps.

It is a further object of the present invention to provide a logic circuitry operating on a timed sequence for rejecting or accepting the bill in accordance with certain dimensional and spacing criteria.

It is another object of the present invention to provide logic circuitry for insuring the accuracy of the bills counted as they are removed after sorting.

It is another object of the present invention for providing logic circuitry overriding certain selection sequences in accordance with a desired operation.

In accordance with the foregoing objects, the present invention utilizes an electronic verification and control system for securing an input count analysis of input bills for various entry conditions and their state of fit ness, and automatic separator insertion for packaging bills in a desired quantity for delivery.

The system includes means for entering the quantity ofa block of currency, commonly referred to as a strap, in terms of the number of bills contained within the strap. A detection circuit detect various entry condi tions and determines quality and fitness. Bills are sorted accordingly, and a total count is maintained. The entry is monitored for condition factors such as bill size, dou ble bills, or bills too closely spaced, which provides for rejection of improper entry as well as inhibiting the operation of the input count for consistency. Verification of input count is provided by further count detection in the area of collection. Sorting, in accordance with detection and gating of the fit and unfit bills is also provided, as well as individualized count control and display. Consistency of strap size is maintained by automatic insertion of card separators between straps in accordance with a desired strap size. A logic system activates machine control sequences in accordance with strap size data provided by tracking the input count and checking for a comparison. Separator control provided by logic responsive to the count in the collector area, also in accordance with the strap size data.

In addition, override controls are provided for allowing the manual insertion of a rejected bill. Since demonetization is effected by print sequences, for demon- 3 etization control, preprint and postprint detections are provided along with logic activating the system for controlling machine operation in accordance with improperly sensed preprint and postprint detection.

The foregoing objects and brief description of the present invention will be set forth in greater detail in the following more detailed specification and the appended drawings wherein FIG I is a perspective view illustrating the functional relationship of the apparatus of the present invention,

FIG. 2 is a generalized electronic system diagram explaining the control interrelationships of the present invention.

HG. 3A is a detail of the input and control logic,

FIG. 3B is a timing diagram related to FIG. 3A,

FIG. 4A is a detail of the stacker detection and counting logic,

FIG. 4B is a timing diagram related to FIG. 4A,

FIG. 5 is a detail of the preprint and postprint detection and control logic,

FIG. 6 is a detail of the override logic,

FIG. 7 is a detail of the input quality detection circuit,

FIG. 8 is a view of a segment of a demonetize bill,

FIG. 9 is a schematic diagram of a preprint detection circuit arrangement, and,

FIG. 10 is a schematic diagram illustrating modifications to the circuit of FIG. 9 for providing postprint de tection.

The introduction and the progress of bills through the apparatus will be described generally with reference to FIG. 1. Individual bills I7 are removed from a strap of bills 18 by an operator and are manually introduced in a direction along a principle axis 19 of the bill to a scanning head 20. The bills thus introduced are automati cally conveyed through the head 20 and are examined, as indicated in greater detail hereinafter to determine whether the bill is fit or unfit for continued circulation.

After examination, a bill is automatically conveyed from the scanning head 20 through an outlet slit 22 to a transport belt 24. The belt 24 and a guide 23 convey an examined bill through a first doubles directional gate station 25, the function of which is described hereinafter, and then to a second fit/unfit directional gate station 26. The gate station 26 includes a solenoid 28 which actuates a plurality of directional guide fingers 32a and 321:. When aa bill which is being transported to the station 26 has been determined by the apparatus to be fit, the solenoid 28 is energized thereby actuating the fingers 32 and causing the direction of transport of the bill to be directed over a first course indicated by the solid arrows. A bill is conveyed over segments of a first course by a belt transport 34 and guide 35, a belt transport 36 and guide 37, belt transports 38 and 39 which provide lateral translation in the transport of a bill with respect to its initial direction of motion along the belt 24, and a transport belt 40 and guide 41 which transport and deposit a fit bill 17 in an upper stacker of bin 42.

When a bill being examined has been determined to be unfit for continued circulation, the solenoid 28 remains in a deenergized state and an unfit bill is trans ported from the gate station 26 over a second course, indicated by the dashed arrows, through a demonetizing station 44, through a postprint detection station 45, and to an upper stacker or bin 46. A bill is transported over segments of this second course by the transport belt 24 and guide 35 and by the transport belt 24 and a 4 transport belt 47. At the demonctizing station 44, the bill is conveyed between a pair of printing rollers which print a demonetizing marking in ink on the bill. The bill is then examined at the detection station 45 for the presence or absence of a demonetizing marking. The absence of a demonetizing marking indicates a mal function at the demonetizing station 44 and operation of the apparatus is automatically interrupted. However, when a demonetizing marking is determined to be present on the bill, the bill is transported to and deposited in the upper unfit bill stacker 46. During operation of the apparatus, the transport belts are continuously driven and the motion of a bill over the first or second course, and through the various stations, is continuous.

In order to provide an accounting and a verification of the number of bills which are removed from the strap 18, and which are fed to the apparatus, the scanning head 20 and an associated electrical circuit means provide a count, and a display of the count, of those bills which are transported through the head and which are determined not to be double or overlapping. In addition, a counter 48 is provided for counting the num' ber of unfit bills which are transported to and deposited in the upper stacker 46 and a counter 49 is provided for counting the number of fit bills which are transported to and deposited in the upper stacker 42. A visual display indicative of the number of fit bills collected in the upper stacker 42 and unfit bills collected in the upper stacker 46 during the sorting of a strap is thereby provided. When a strap 18 is depleted, and a number of bills equal to a predetermined strap number has introduced into the scanning head 20, the apparatus will automatically transfer into a stop mode. At this time, the operator can, from the displayed counts, verify the number of bills in the strap. When the number of bills entered into the scanning head 20 is less than the predetermined number of bills in a strap, an error of secu rity breach is indicated, and the operation of the rnachine can be terminated until the reason for the discrepancy is determined.

Upon verification, the operation of the apparatus is reinitiated by the operator through actuation of a start switch, which transfers the apparatus into an operating mode. At this time, those bills in the upper stackers 42 and 46 are automatically transferred to lower stackers 52 and 54 respectively by the opening of lower doors in each of the upper stackers. The upper stackers which are then emptied are conditioned to receive fit and unfit bills from a succeeding strap.

The apparatus retains tallies of the number of bills which have been sorted into each of the upper fit and unfit bill stackers 42 and 46, respectively. When this tally of fit or unfit bills is equal to a predetermined strap quantity, a separator card 56 is automatically transferred into an upper stacker 42 or 46. The separator cards 56 are stored in card bins 58 and 60, respectively. A separating card will be transferred to the lower stackers from the upper stackers along with the bills contained therein, upon completion and verification of a strap. After the lower stacker units are filled to capacity, an indication is provided and the unfit bills can be removed and bound into straps for subsequent destruction.

The introduction of bills, under certain conditions, will result in a light transmissivity which is substantially lower than the transmissivity of an unfit bill. This condition occurs for example, when one bill adheres to an other and these doubles" are fed to the scanner head 20. This condition can also occur when bills which are fed seriatim, are fed at a rate which causes them to overlap at the examination station. It is desirable that these bills be inhibited from traversing the first and second courses, and that they be removed from the apparatus and be delivered to a station at which the operator can examine them and decide as to the feasibility of reinsertion. For example, bills which are introduced in an overlapping manner and bills which are lightly ad hering one to the other can be separated and be reintroduced, while bills which cannot be readily separated or bills which are severely soiled can be removed for individual treatment. The apparatus is adapted for sensing when doubles have been introduced into the machine, for diverting their passage prior to reaching the fit/unfit gate station 26, and for returning these bills to a return shelf 62 at the operators station. Those hills which exhibit a substantially low transmissivity conforming to a predetermined doubles reference level (which level is substantially lower than a reference level for distinguishing fit from unfit bills) are detected by the apparatus upon examination by the scanner head 20. A double bill is transported to the double gate statirn 25 at which location solenoid 64 is energized. The energized solenoid actuates a plurality of direction diverting fingers 66a and 66b. As a double bill is transported from the slot 22 by the belt 24 and guide 23, its direction of transport is altered by the fingers 66a which cause it it travel over a course indicated by the curved dashed line between a return roll 68 and guide 69 to the return tray 62. The apparatus inhibits entry of a count into the strap counter and strap count verification is not affected. Those returned double bills which cannot be re-entercd because of their condition, are available to the operator for accounting when verifying the total number of bills derived from a strap 18.

It is desirable, for security reasons, that the apparatus recognize when a bill which is demonetized is fed to the apparatus. The scanner head includes a detection means for sensing the presence of a demonitizing marking on a bill at the examination station. When this marking is detected, the apparatus is automatically transferred into a stop, locked mode and the apparatus cannot be restarted without the actuation of a keylock, the key for which is maintained under the control a supervisory operator.

In addition to United States currency, the Federal Reserve Banks are required at times to process other special forms of value paper such as Treasury Notes, Food Stamps, etc. While processing of this value paper generally does not require separation based on fitness, the paper is handled in straps and generally requires counting, verification, forming into straps and at times "devalueing. The apparatus illustrated in FIG. 1 includes a second scanning head 70 to which this special paper is fed for processing. The scanning head 70, for value paper, operates as a strap counter detector. After the paper is examined, it is conveyed from an exit aperture 71 and is transported by a belt 72 over a course indicates by solid arrows to an upper stacker 76. For purposes of simplifying the drawing, the additional belt and guides for transporting the paper over the course is not illustrated but it is understood that guides equivalent to the guides 23, 35 and 69, and a transport belt equivalent to the belt 47 which are employed with belt 24, are similarly employed with the transport belt 72. A counter detector 77 is provided for sensing paper which is transported to, and deposited in, the upper stacker 76. When the transmissivity of the document is less than the pre-established doubles reference, a double gate station solenoid 78 is energized for actuating direction diverting fingers 80 and diverting the transport of the paper to a return tray 77. Those documents which are introduced into the upper stacker 76 are transferred to a lower stacker 78, when a number of value papers equal to the number in a desired strap have been deposited in the upper stacker. In addition, a separator card 56 from separator bin 80 is deposited in the upper stacker 26 when a number of papers equal to the strap number have been sorted and is transferred with the value paper in the upper stacker to the lower stacker 78. A doubles transport arrangement, which again for the purpose of simplifying FIG. 1 is not illustrated, is understood to include a roller, guide, and a return tray equivalent to the roller 68 and guide 69 and return tray 62.

In addition to that portion of the apparatus which has been described generally thusfar with respect to FIG. 1, there is also provided circuit means for causing various machine operations in response to the information contained in signals received from the scanner and the various detectors. The circuit means, which is described in greater detail hereinafter, operates to effect operation of the doubles gate station 25, operation of the fit or unfit gate at station 26, operation of the strap card separator, transfer of the bills in an upper stacker to a lower stacker, and causes the machine to transfer from an operating mode to a stop mode. The change of modes is effected when a number of bills equal to a pre determined number of bills in a strap has been introduced and sorted by the apparatus, when a malfunction in the demonetizer is detected, or when a demonetized bill is introduced into the apparatus.

Referring now to FIG. 2, the generalized system block diagram detailing the functional interrelationship of the electronic components of the apparatus is indicated. The major counting system is illustrated as block I10 which provides a totalized count of the strap input and display therefor. Strap size is provided as an input to the strap input counter along the line 112 from the strap size input device 114. Adustment of the strap size input device 114 in accordance with the number of bills in a particular strap thereby indicates to the strap input counter the total number of bills to be expected as a strap input condition. Activation of the strap input counter is in response to bills placed along the regular bill input line 116 or the special bill input line 118 through the entry detection and logic circuit 120. Sensing of the various entry conditions in accordance with the entrance of the bills along the input lines 116 and 118 will provide the appropriate decision within the entry detection logic circuit 120 for providing indication as to whether the bill is to be rejected. lfa regular input bill is not rejected, it will be further classified as a fit or unfit bill. If the bill is to be rejected, for example as a double, an appropriate signal is provided along the line 122 to the double gate and solenoid control cir cuitry 124 which in turn operates the appropriate doubles gate for regular or special double conditions as illustrated in FIG. 1. In addition, rejection of a bill will also be placed along the line 126 for inhibiting the strap input count and display 110. Thus, a rejected bill is not counted as an appropriate input on the strap input counter 110.

If the bill provided along the regular input I I6 is categorized as not falling within one of the doubles gate activation categories, the bill is then examined for quality. If the bill is determined to be unfit, an appropriate logic signal is provided along the line 128 to the fitunfit solenoid control 130 which, in accordance with the detected quality condition of the bill as in its unfit state, provides an appropriate control to the fit-unfit control gate illustrated in FIG. 1. As each appropriate selection is made, the bills are stacked in their appropriate stackers. A regular bill is stacked in either fit or unfit stacks, while a special bill is merely stacked without quality analysis.

Sensors positioned at each appropriate upper stack provide a signal corresponding to inputting of each stacked bill. Thus, the appearance of a fit bill at the fit bill upper stacker will provide a logic signal along the line 132, an unfit stacked bill will provide a logic signal along the line 134 and a special stacked bill will provide a logic signal along the line 136.

The stack signals are fed to a stacker detection logic circuit 138 which provides appropriate output signals along the output lines 140 to a counter unit 142 which consists of individual counters 142A, 1423, and 142C, for counting each fit, unfit, and special bill as they are collected. In accordance with the predetermined strap size information provided from the strap size unit 114 along line 144 to the counter display logic unit 142, the separator control 146 will be activated in accordance with the completion of a strap count in any one of the fit, unfit, or special counters. The appropriate separator control illustrated generally as 146 will thus be activated in accordance with achievement of a strap count in any of the counter units described generally in the block 142, causing activation of the separator mechanism inserting a separator card into the proper upper stacker as was described in conjunction with FIG. 1.

Completion of the predetermined strap input count in the counter 110 will provide an appropriate logic sig' nal along the line 147 indicating a strap full condition to a system control unit 148. The effect of the strap full signal along the line 147 to the system control unit 148 will result in stopping further bill feed into the machine. This machine feed shut down is accomplished by an appropriate output signal provided along the line 154 to a machine control operating mechanism 156. Mechanism 156 provides the input drive stop feature necessary for the accomplishment of this function. Reactivation of the machine by activation of the full input signal to the system control unit 148 will provide an output signal along the line 150 to the stacker door control 152. The function of the stacker door control will be, as described in FIG. 1, to open the doors on each of the upper stackers described in FIG. 1 and permit the bills thus far accumulated in the stackers to drop into the lower stacker. The FULL 151 will also reactivate the feed control mechanism block 156.

Since the strap size data from unit 114 has also been entered into the block 142, the separator control 146 will cause the appropriate separator card to drop into the appropriate upper stacker when a full strap size is achieved in any of the fit, unfit or special stacker units, respectively.

As was set forth above, the machine includes a demo nitization function. It is thus important to monitor two conditions: first, whether a demonetized bill is being scanned (pre print detection) and; second, whether the printing equipment is working properly (post print). in the first condition, a signal from the pre-print scanner is analyzed to determine whether an entered bill has be demonetized. if it has, a logic signal applied along line 158 to the system control 148 activates a shut down sequence to machine control unit 156. This will disable both input feed drive and main motor drives, shutting down the machine. An alarm light or other indication may also be provided. in the second condition, a signal from the post-print scanner is analyzed to determine if the bill has been properly demonetized. If it has not, a logic signal is applied along line 160 to the system control 148 to activate a shut down sequence to machine control unit 156. This will first disable the input feed drive and, after a delay sufficient to allow previously demonetized bills to exit the machine, shut down the main motor drive.

Reactivation of the machine after a pre-print or postprint shut down is effected by depressing the RE- START control 153 which resets the system control 148 and permits reactivation.

As was set forth above, activation of the doubles gate will result in rejection of a bill. The options available to the operator after rejection, include reinserting of the bill, in which event the machine merely functions as it did in the previous cycle, or activating a machine override. The purpose of the machine override will be to automatically demonetize a bill without the improper entry or quality decision features described above. Thus, activation of a doubles override 164 by means of appropriate input 162 provides an appropriate signal along the line 166 to both clamp the doubles gate 124 so as not to reject the bill, and the fit/unfit gate solenoid control 130 so as to pass the bill through the demone tizing section described in FIG. 1. The operation of the logic override 164 in this doubles mode is set by the input 162, and triggered upon receipt of a signal indicating that the now entered bill has reached the proper position within the sensing head. The trigger signal is provided from the entry condition detection circuit along the line 168. The operation can only be accomplished once for each double override. Resetting of the override entry bill is fed into the unfit stacker detector as indicated by the appropriate signal then applied along line 134 to the stacker detection logic 138 and along the output line 170 to the override logic 164.

A supplemental override operation is provided by means of the override input 172. The function of the override input 172 is to demonetize the special bills. In this instance, activation of 172 will provide an appropriate signal to the override logic 164 for again deactivating the doubles gate and clamping the fit/unfit solenoid control to its unfit condition. In this mode, however, accumulation of demonetized specials is accomplished in the unfit stacker and operates continuously without reset until the specials override function 172 is again activated, thereby placing the override logic 164 in its initial condition.

The demonetization of special bills is accomplished after collection of specials in the specials stacker. Demonetization of specials is effected by re-feeding stacked specials into the Regular input, again with the doubles gate clamped to prevent rejection, and with the fit/unfit gate clamped to the unfit position. To prevent erroneous counts, the override logic will provide an inhibit signal along line 174 to the strap input counter 110 upon activation of the specials override function 172. This will inhibit recounting of specials for demonetization.

Referring to FIGS. 3A and 31! detail logic circuitry for the input function is described. The input logic performs two functions, entry conditions rejection and quality determination. For entry condition analyses, the input logic acts, to activate the doubles gate, in accordance with certain undesired conditions. These conditions include (a) detecting a double within the scan head itself, (b) detecting whether a bill is too long, (c) detecting whether a bill is too short, and (d) detecting whether two bills have been fed too closely to each other, In any of these situations, the doubles gate is activated and the bill is rejected. In the case of bills too close to each other, both forward and rear bills are rejected. It is noted that both the regular and special entry condition detection, logic and rejection mechanism are precisely the same. The only distinction between the regular and special input systems resides in the quality detection scheme, lacking in the special input system. Thus, FIG. 3A illustrates the entire logic, selection and decision making function for the regular input scheme, it being understood that the special input circuits are the same with the exception of the absence of quality detection and selection. With specific regard to FIG. 3A and the timing diagram, FIG. 3B, the regular input logic signal is provided by means of fluorescent light source 200 applying appropriate signals to the detector 202, the signals therefrom fed in turn to a quality and input detection circuit 204, set forth in greater detail below. It will be further understood that this circuitry may also be duplicated in connection with the special detection head, with the quality detection position thereof omitted or ignored. A clock source, CLK, not shown, supplies clock pulsing CL at various points within the logic. The detection circuit 204 provides a quality indication along line 205, a BILL PRES- EN'I' along line 206 and a doubles indication along line 207 to gate 208. For logic purposes, a BILL PRESENT is a logical one, a FIT is a logic I, and the presence of a DOUBLE a logic 0. The detection circuit 204 determines the presence of a bill and applies a high condition BILL PRESENT signal along the line 206 to the .II( flip-flop 209, and on the appearance of the first clock pulse thereafter causing the output of the flip-flop 209 to go high. The term "high will be understood to include the meaning of a logical l and low, logical '0'. It will be understood that reverse logic may also be employed. Upon the appearance of the next clock pulse, the 0 output of the flip-flop 210 having a high state on its J input will also go high, thereby applying a high signal from the 0 output of the flip-flop 201 to the J input of the flip-flops 212 and 214. On the third clock pulse, the flip-flops 212 and 214 will each have their respective Q outputs go high, and their 6 outputs go low.

A counter 216 is provided which is maintained in a normally disabled condition when a high signal is placed on its clear input CLR along the line 218 from the 0 output of flip-flop 314. When the flip-flop 214 is set by the third clock pulse as described above, the Q output of flip-flop 214 will go low, thereby enabling the counter 216 which will begin counting clock pulses introduced along the line 220. The counter 216 is designed to establish in conventional manner, output conditions corresponding to predetermined counts.

The entry condition logic scheme of the present invention employs the use of pulse sequence timing over a fixed duration to determine the minimum length, maximum length, and inter-bill spacing decision features described above. By way of example, the logic of the present invention establishes a pulse count of 150 pulses representing an approximately length of an average bill, 6% inches. A window may be established on either side of the average pulse position to define a gate length condition for a correct range of bill lengths. Again by way of example, a gate length may be established anywhere between a lower limit count of I47 pulses and an upper limit count of I53 pulses representing the minimum and maximum desirable length of a bill to be accepted by the machine. Bills passing in less time than the minimum or more time than the maximum are to be rejected. Along the same lines, an inter bill spacing definition can be established utilizing the same count frame. Thus, taking into account the timing and speed of the feed mechanisms and scan operation, a condition of N machine pulses is defined from the first sensed bill until the machine is ready to receive another bill. In the example given, N is set equal to 200 machine pulses or about 8 inches in terms of feed dis tance. Since a bill averages about 6 :4; inches, by establishing a 200 pulse spacing as a minimum cycle between bills, an inter-bill spacing definition of about 2 inches may be established. Obviously, other interbill spacing criteria may be employed, and the use of 200 is illustrative only and not intended to be limiting.

Referring again to FIG. 3A, the counter 216 provides the pre-set count level signals. An output along the line 222 thus corresponds to the lower limit count, an output along the line 224 corresponds to the upper limit count and an output along the line 226 corresponds to the 200 count.

The Q outputs of the flip-flop 209 and 210 and the Q output of flip-flop 212 are connected to a futher gate 228. At the time of the activation of the third clock pulse, which is also connected to gate 228, all of the inputs to the gate 228 are high, thereby resulting in a low output from the gate 228, which is in turn inverted in the inverter 230 providing a high output along the line 232. This high output along the line 232 represents the start of bill SOB pulse, shown in the timing diagram FIG. 3A.

When the bill ends, the BILL PRESENT signal on line 206 goes low, signifying the bill is no longer present. At the next clock pulse, the flip-flop 208 is rest. Thus, after a further three pulse delay, (FIG. 3b), the gate 238 is activated with three high inputs from the 6 side of flip-flops 209 and 210, and the 0 side of flipflop 212, and the next following clock pulse. This causes a low condition at the output of the gate 238. The low is inverted in the inverter 240 and a high signal, representing an end of bill pulse EOB, appears along the line 242. If the EOB pulse occurs before the lower limit count has appeared along the line 222, the flip-flop 244 will not have been placed in its set condition, meaning the 6 output of the flip-flop 244 will be high thus conditioning the J input of the flip-flop 246. The appearance of the E08 pulse along the line 242 to the clock input of the flip-flop 246 will thus cause the flip-flop 246 to become set, thereby placing a low output along the 0 line 248 of the flip-flop 246. The low output will proceed along the line 250 to the NAND gate 208. The low input to the NAND gate 208 will result in high input along the output line 252 of the NAND gate 208. The operation of the effect of the output along the line 252 will be described in further detail below; however, suffice it to say at this point that the effect of the high NAND gate 208 output signal in any event will be to reject a bill by allowing the activation of the doubles gate, in this example for a bill short condition. in addition, the output line 248 of the flipflop 246 can also be coupled along the line 254 to a bill short indicator 256. If the end of bill pulse had arrived after setting the flip-flip 244, meaning the minimum bill length was surpassed, the flip-flop 246 would not have been preconditioned and thus would not have been set to provide the bill short indication.

The ultimate length of the bill length gate is set by the ultimate length count appearing along the line 224. More specifically, a low condition along the line 224 indicates achievement of the ultimate length count, the low being converted into a high condition through the inverter 258 for driving the flip-flop 260 into its set condition thereby placing a high condition to the flipflop 262. Appearance of the end of bill pulse along the line 242 after the flip-flop 262 has been conditioned with a high at its J input results in the 6 of flip-flop 262 state going low. Appearance of the low signal along the line 262 will be passed along the line 266 and to the NAND gate 208, where it will result in a high condition along the line 252. Effect of this high condition, as described above, will be to activate the doubles gate. In addition. the signal along the line 264 may be fed along the line 268 to a bill long indicating device 270, thereby providing the operator with an indication that the bill was rejected for reasons of undue length. It is again noted that had the end of bill pulse appearing along the line 242 occurred prior to the time the ultimate length count signal appeared along the line 224, the flip-flop 262 would not have been pre-conditioned and the 6 state would have remained high thus blocking a rejection condition.

The bill length long and short indications are also provided by a backup logic system including the gate 272 coupled to the high output of the flip-flop 244 and the low output of the flip-flop 260 respectively. Thus, the gate 272 defines the window condition representative of the bill length gate. The output of the gate 272 through the inverter 274 is used to condition the flipflop 276 to respond to any end of bill pulses received during the window condition defined by the minimum and ultimate length. Thus, and end of bill pulse applied along the line 242 to the clock input of the flipflop 276 during the period before the beginning or after the end of the bill length gate keep flip-flop 276 in reset state, providing a low signal along the line 278 which will be applied in turn to the NAND gate 208. The low condition will result in a high condition along the output line 252 indicating that a bill which is either beyond maximum or below the minimum length has been detected.

The output line 226 of the counter 216 goes low upon achieving a count indicating the minimum desired inter-bill spacing, in this example, a 200 count. Prior to the time a 200 count is achieved, the flipflop 280 is in a reset condition with the 6 output high. When the 200 count condition is received along the line 226, the flipflop 280 goes into its set condition, and the output 6 of the flip-fiop 280 goes low. The low output is converted by the NAND gate 282 into a high and is inverted in the inverter 284 to a low condition. The low condition is fed back to the reset input of the flipflop 214, thereby ending the cycle by driving the flip-flop 214 to its reset condition. The reset signal is also applied along the line 286 to the quality and input detection circuit 204 for reasons which will be described in further detail below with reference to that circuit.

The resetting ofthe flip-flop 214 causes the output of the flip-flop 214 to go high, thereby clearing the counter 216 along the line 218. A high condition on the clear input of the counter 216 also inhibits the futher count of clock pulses appearing along the line 220 as was described above. The high 6 signal from flip-flop 214 is also applied along the line 288 through inverter 289, to the reset inputs of each of the flip-flops 234, 244, 260, 246, 262 and 276 for resetting each of these flip'flops, which are reset by a low input condition at the R inputs. If, however, the system is in a condition where an end of bill pulse has already appeared along line 242 and a new start of bill pulse is applied along the line 232 prior to the 200 count along line 226 being achieved, it will be apparent that the flip-flop 234 will be set to respond to the new start of bill pulse appearing along the line 232 when applied to its clock input by changing states, rendering its 6 condition low. This low 6 condition of flip-flop 234 will be applied to the NAND gate 208 along line 235 which will apply a signal to the line 252 resulting in a reject by activation of the doubles gate. It will be recalled that prior to the end of the 200 count, the Q output of the flip-flop 224 is high, applying a high to the .1 input of flip-flop 234. Thus, appearance of the start of bill pulse along the line 232, and coupled to the clock input of the flip-flop 234, will cause the output of the flip-flop 234 to go high, thereby causing the flip-flop 236 to receive a high on its J input. The flip-flop 236 will remain, however in its reset position with its Q output high until a high is received on its clock input. Since the flip-flop 236, which is coupled to the flip-flop 234, will have its J-K inputs set to the state that will enable the 200 count signal appearing along the line 290 to place flip-flop 236 in its set condition, the flip-flop 236 thus applies a low condition along its 6 output into the NAND gate 208. Therefore, as a result of the action of the flip-flop 234, the first bill be rejected, and as a result of the action of the flip-flop 236, the second bill which has been following too closely to the first will also be rejected. Flip-flop 234 will be reset by the 200 count as described previously thus setting the .l-K inputs to the flip-flop 236 to the state which will enable the next 200 count along line 290 to place it again in reset condition.

Referring again to FIG. 3A, the activation logic of the mechanical gating operation is built around the operation of a shift register, operable to shift bits along a se quence of stages in known manner, in accordance with a predetermined clock sequence. As shown in FIG. 3A, the first shift register 300 corresponds to the doubles solenoid gate selection circuitry, and a second shift reg ister 302 corresponds to the fit/unfit gate solenoid gate selection circuitry. in terms of machine feed sequence operation, it is the doubles selection which is made final, and then the quality selection. Each shift register includes a gate input 304 and 306 respectively for gating in a clock signal identified as CLK2. The rate of the clock signal is at a slower rate than the clock pulses described above in connection with the timing frame, and by way of example, this example may consist of a rate of l clock pulse per half inch of linear feed. The timing of this clock pulse is to permit the appropriate fit or unfit gate or doubles gate selection to be made when the bills have reached a position in the feed line such that activation of the gates will be at the proper time to reject the bills. Generally speaking, the operation utilizes deactivation of a present input condition to pre vent rejection. for the doubles gate, and unfit selection, for the fit/unfit gate. in each case, the shift registers each shift an input pulse for a predetermined time. If

13 the time is achieved without the shift register being cleared, the appropriate gate activation occurs. For the doubles gate, rcjcction occurs. and for the fit/unfit gate, an unfit selection is made. If the other choice is made, the register is cleared prior to the predetermined time period.

Referring again to FIG. 3A, gates 304 and 306 are each activated by means of a BILL IN low signal which may be derived from the 6 output of the flip-flop 214, and which is low for a 200 count as explained above. Upon the opening of the respective gates 304 and 306, the shift registers 300 and 302 each begin to shift the BILL IN pulse along the length of the respective shift registers. in the direction of the arrow. at a rate in accordance with the clock pulse rate CLKZ.

Regarding the gate logic, more specifically, the activation of the doubles gate shift register 300 begins the doubles gate timing cycle. Activation occurs by shifting the logical ones into the shift register 300 when the gate 304 is uninhibited. This occurs when a low condition representing BILL IN is applied along line 308 to the inverter 307. The low is thus applied as a high to the gate 304 and thereby allows the shift register 300 to shift logic ones therealong, in the direction of the arrow, until a stage, designated as X. is reached.

Similariy, activation of the fit/unfit gate shift register 302 begins the quality control timing cycle. Activation occurs by shifting the logical ones into the shift register 302 when the gate 306 is uninhibited. This occurs when the low condition representing BILL IN is applied along line 308 to the inverter 309. The low is thus applied as a high to the gate 306 and thereby allows the shift register 302 to shift logic ones therealong, in the direction of the arrow, until a stage designated as Y, is reached.

Referring again to the doubles timing, the shift register 300 includes a clear input CLR. Assuming no clear pulse, in the form of a low condition, is applied along line 310 to clear the register 300, the shifted logic ones, upon reaching the stage X, will be applied along the line 314 to set the flip-flop 316. Since the side of the flip-flop 316 is connected to the NAND gate 318, a high condition is applied. The gate 318 also receives an input along line 319 and termed DOUBLE AND SPE- CIAL OVERRIDE, the function of which will be set forth in greater detail in the description of FIG. 6. The input 319 is normally in a high condition. The high output from the flip-flop 316 therefore results in a low output condition applied to the drive circuit 320. Since the drive circuit is designed to respond to a low condition. the application of the low condition will in turn activate the doubles gate 322 causing the doubles bill to be rejected. The doubles gate 322 corresponds to the regular bill solenoid mechanism 64, shown in FIG. 1. The special bill solenoid mechanism 78 is activated in precisely the same manner by corresponding logic circuitry, now shown for ease of illustration.

The use of the override line 319 is designed to clamp the doubles gate 322 to its acceptance position. Thus, applying a low condition along line 319 will clamp the output of the NAND gate 319 to a high condition, regardless of the condition of the other input to the gate 319. The high condition will inhibit the driver 320 and thus prevent switching of the doubles gate solenoid 322 from its acceptance position to its rejection position.

Referring to the fit/unfit timing, the shift register 302 also includes a clear input CLR. Assuming no clear pulse, in the form of a low condition, is applied along line 326 to clear the register 302, the shifted logic ones, upon reaching the stage Y, will be applied along the line 336 to set the flip-flop 332. Since the 6 side of the flip-flop 332 is connected to NAND gate 334, a low condition is applied. The low condition results in high condition from the gate 334 which is inverted to a low by the inverter 336. The drive circuit 338, as before with respect to drive circuit 320, responds to a low con dition for activating the fit/unfit gate 340, causing the same to switch from its acceptance or fit position to its unfit or rejection position, causing the bill to be fed to the printer (demonitizing) mechanism. The fit/unfit gate 340 corresponds to the quality gate solenoid 28, shown in FIG. 1.

It is noted, from FIG. 1, that the quality gate solenoid 28 is farther downstream from the doubles gate solcnoid 64. Thus, the selection of the solenoid 64 must occur at a later point in time than the selection of the solenoid 28. This is accomplished by virtue of the X and Y stage selection in shift registers 300 and 302 respectively. The X stage is thus selected as a stage earlier in the stage sequence of shift register 300 than the Y stage in shift register 302. Since both shift registers are activated simultaneously. and shifted at the same rate by CLK2, the selection of the later Y accomplishes the timing differential. For example, the X stage may be 8 stages earlier than the Y stage. If the rate of shifting is one pulse per V; inch of feed, then 4 inch distance elapses between successive selections. Other variations of timing sequence are of course possible, the foregoing being intended as exemplary only and not limiting.

The NAND gate 334 includes a further input 342 corresponding to the signal applied to the line 319, DOUBLES AND SPECIALS OVERRIDE. The override signal is a clamping signal, normally high. Should the clamping of the fit/unfit gate 340 in its unfit condition be desired, a low signal is applied along the line 342, clamping the output of gate 334 high. The output of gate 334 is inverted in inverter 336 to a low which in turn drives the drive circuitry 338. The drive 338 activates the fit/unfit gate 340, causing the solenoid 28 to go into its unfit condition, passing bills to the printer.

The operation of both doubles gate and quality gates are inhibited by clearing the respective shift registers 300 and 302. Inhibiting its accomplished by a sampling operation at a timed position. Since the sampling system must allow sufficient time for a bill to pass the scan head. 20 or 70, and be analyzed. the 200 count signal can be employed. Thus, referring to FIG. 3A, the 200 pulse signal is derived from the counter 216 and applied as a high signal from line 290 to line 343 to NAND gate 344, where it is gated with a clock pulse to provide a low signal of one clock pulse duration to the inverter 345. The resulting high signal is applied both to NAND gates 346 and 347.

The high inputs to gates 346 and 347 provide sam pling pulses to determine the selection conditions. Referring first to the doubles selection, it was pointed out above that the presence ofa high condition on the line 252 from the gate 208 indicated a double gate activation for rejection. Thus, to activate the doubles gate, it is necessary that the shift register 300 is not cleared while a high condition remains on line 310. Thus. if a rejection is to occur, line 252 is high. applying a high condition to one input of the NAND gate 348. The other input 349 to NAND gate 348 is a DOUBLE OVERRIDE condition which will be explained in further detail below. Normally, the double override condition on line 349 is high. Thus, a low signal results from gate 348 and is applied to gate 346, thus clamping the output of the gate 346 to a high condition and inhibiting the shift register 300 from being cleared, thereby resulting in activation of the doubles gate 322 when the shifted logic one signal reaches line 314 at stage X as described above.

If no entry condition requiring bill rejection through the doubles gate occurs, the line 252 remains low, thus maintaining the output of gate 348 high. When the high sampling pulse is applied at the 200 count to the gate 346, the gate 346 passes the sampling pulse as a one clock pulse duration low signal on line 310, thereby clearing the shift register 300 and resetting the one logic conditions to zeroes, preventing activation via line 314.

The quality sampling test condition samples the other input to the gate 347. Thus, when the scan head and quality detection circuit 204 determines that an unfit bill is present, a low input is provided along the REG FIT line to the gate 347. The low condition clamps the output of gate 347 to a high condition, thereby maintaining the high signal on line 326, preventing the shift register 302 from clearing, and resulting in activation of the quality gate 340. When the shifted logic one signal reaches line 330 at stage Y as described above.

If no quality factor rejecting the bill occurs, the line REG FIT is high. At the appearance of the sampling pulse from gate 345, a one clock duration low condition will be applied from gate 347 along line 326, clearing the shift register 302 and preventing activation of the fit/unfit gate 340, thereby holding the gate in its fit or acceptance condition.

In both regular and special bill inputs, it was noted above that the strap input counter 110 does not count a bill rejected for reasons of failure to meet an entry condition. The logic design shown in FIG. 3A permits this operation to occur by deriving a signal from line 310, corresponding to the doubles clear signal, for incrementing the counter 110. Since the strap input counter should count only acceptable bills, use of the clear signal along line 310 to increment counter 110 is appropriate. The incrementing signal is derived from line 310 and applied along line 126 to counter 110.

Referring now to FIG. 4A and 4B there is shown a detail of the stacker detection and counting logic. As was noted hereinabove, each of the upper stackers includes sensing means for providing an indication of the injected presence of the bill therein. These signals are representative of the presence of the bill in each of the upper stackers for fit, unfit or special bill accumulation. As is noted in connection with FIG. 2, the indication of a fit or special bill is provided along the respective input lines 132, 134 or 136. The input lines are coupled to detection logic 132A, 134A and 136 respectively.

Referring now in greater detail to the fit stacker de' tection logic 132A, the input signal applied along the line 132 is applied to the inverter trigger 350. The inverter trigger 350 will switch to low output condition 350A at T of proper shape and magnitude when the leading edge of a bill passes through the fit stack detec tor located at the leading edge of the fit upper stacker as described above, and remains in this condition for as long as the bill is present. This signal is inverted in inverter 352 to a high signal which is applied at the input of the gate 354. Assuming for the moment the other input of the gate 354 to also be high during the application of the stacker detection signal from the inverter 352, the leading edge of the resulting low output signal 354A from the gate 354 will provide a negative going differentiated output spike 356A from the differentiator 356 which is applied to a time delay trigger 358. The time delay trigger 358 is designed to respond only to negative going spikes to provide a gating signal 358A immediately upon excitation by an input thereto, and is further designed to maintain the gating signal 358A for a specific time. The trigger 358 may be a conventional monostable multivibrator. The signal 358A sets the synchronizer delay 360, which in turn synchronizes the system with a clock signal supplied along the line 363 and to provide a three pulse delay in order to synchronize the stacker count with the input count in accordance with the three pulse delay provided by flip-flops 208, 210 and 212 described in connection with FIG. 3A. The synchronizer can in fact be constructed of sequential flipflops acting sequentially. as was described in FIG. 3A, and as shown as including JK flip-flops 361 and 362.

In operation, the function of the time delay trigger 358 is to provide an additional count pulse to the flipflop 364 in the event that the passage of bills through the feed mechanism results in 2 bills being so closely overlapping as they are applied into the upper stacker that only a single count pulse is applied along the line 132. Since verification is an important feature of the present invention, some means must be provided in order to insure that two counts are provided where two bills are placed into the upper stacker even though the upper stacker detection only detects a single bill because of a partial overlap between bills. By way of example, an average bill can have an average detectable length of milliseconds, the delay period placed into the time delay trigger 358 is of a time sufficient for insuring that a second pulse will pass through for counting purposes, if that average length is exceeded. By way of example, the present invention may utilize a time delay of milliseconds.

The setting of the first flip-flop 361 by the output gate 358A of the trigger causes the output signal 361A of flip-flop 351 to go high after the next clock pulse, setting the next flip-flop 362. The flip-flop 362 output signal 362A goes high after the next clock pulse, and finally. the flip-flop 364 output 364A goes high after the third clock pulse. Just prior to this point, however, the gate 365, which is tied to the Q outputs of flip-flops 361 and 362, and to the 6 output of flip-flop 364, is set to pass the third clock pulse as output signal 365A. The output signal 365A is passed along line 366 to increment the fit counter register 368, indicating a bill received at the fit bill upper stacker.

After the delay time of the trigger 358, the trigger signal 358A will return to its low condition. As a result, as 3 clock pulses successively are applied, each flip-flop 361, 362 and 364 will return to reset conditions. Just prior to flip-flop 364 going low, however, the third clock pulse after the gate 358A goes low will pass the gate 367, as signal 367A, the gate 367 being previously conditioned by the Q outputs of flip-flop 361, 362, the 6 output of flip-flop 364. The output of the gate 367 forms the other input of the gate 354.

At the moment T; when the pulse 367A is applied to the gate 354, two events are possible. First, a bill of proper duration has entered the stacker, leaving the sensor area, and no bill is present. In this case, the output along line 132 is low, and the other input to the gate 354 is low, clamping the output of the gate 354 high. 

1. A circuit arrangement for detecting the passage of an article bearing a repetitive marking adapted to repetitively alter the reflectance of light impinging on the marking as the article is transported through an examination station, comprising: a first circuit means including a photosensitive device positioned at the examination station for receiving light which is reflected from an article being transported through the station, said first circuit means generating an alternating signal as the article is transported through the station, said signal having a frequency corresponding to a frequency of the repetitive markings on the article; integrating circuit means operatively connected to said first circuit means for providing an output signal during the transit of an article having no repetitive marking thereon through the examination station, and for providing substantially no output signal during the transit of an article having a repetitive marking thereon through the examination station; a second circuit means for providing a signal for disabling said integrating circuit means in the absence of an article at the examination station, and for enabling the integrating circuit means to provide the integral of said alternating signal during the transit of said article through the examination station; comparator circuit means having first and second input terminals, said comparator circuit means providing a first DC output level when the amplitude of a signal applied to said first input terminal is less than the amplitude of a reference signal applied to said second input terminal; interconnecting means for applying the integrated signal from said integrating means to the first terminal of said comparator; and means for applying a reference signal to said second input terminal of said comparator.
 2. The apparatus of claim 1 wherein said second circuit means for enabling said integrating circuit means comprises means for enabling said integrating circuit means for an interval of time which occurs coincidentally with, but is less in duration than, the transit time of an article through the examination station.
 3. The circuit arrangement of claim 1 wherein said alternating signal exhibits a sinusoidal waveform, and including a third circuit means operatively connected between said first circuit means and said integrating circuit means for filtering and shaping said alternating signal to provide a substantially square wave signal for application to said integrating circuit means.
 4. The apparatus of claim 3 wherein said third circuit means for filtering and wave shaping comprises active filter circuit means coupled in cascade with a second comparator circuit means, and means for establishing a reference potential for said second comparator means. 